-- Copyright (c) 2010, Pavel Kovar
-- All rights reserved.

---------------------------------------------------------------------------------------
-- This file is a part of the Witch Navigator project

-- nco_phase
-- Impleented
--   * 6x numerical controlled oscillators for carrier removal
--   * 6x complex mixer
--
-- Consecutive processing in single HW 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
-- library UNISIM;
-- use UNISIM.VComponents.all;

entity nco_phase is
    Port ( b_phase : in  STD_LOGIC_VECTOR (31 downto 0);
			  clk_dsp : in STD_LOGIC;
           sin_out : out  STD_LOGIC_VECTOR (7 downto 0);
           cos_out : out  STD_LOGIC_VECTOR (7 downto 0);
           nco_phase_out : out  STD_LOGIC_VECTOR (31 downto 0));
end nco_phase;

architecture Behavioral of nco_phase is

signal accreg0, accreg1, accreg3, accreg4, accreg5: std_logic_vector(39 downto 0) :="0000000000000000000000000000000000000000" ; 
signal a_reg1: std_logic_vector(31 downto 0) :="00000000000000000000000000000000";
signal sin_pom, cos_pom: std_logic_vector(7 downto 0);

component phase_acc
	port (
	a: IN std_logic_VECTOR(31 downto 0);
	b: IN std_logic_VECTOR(39 downto 0);
	clk: IN std_logic;
	s: OUT std_logic_VECTOR(39 downto 0));
end component;


component sinrom
	port (
	clka: IN std_logic;
	addra: IN std_logic_VECTOR(7 downto 0);
	douta: OUT std_logic_VECTOR(7 downto 0));
end component;

component cosrom
	port (
	clka: IN std_logic;
	addra: IN std_logic_VECTOR(7 downto 0);
	douta: OUT std_logic_VECTOR(7 downto 0));
end component;


begin

process (clk_dsp)
begin
	if clk_dsp'event and clk_dsp = '1' then
		a_reg1 <= b_phase;
		accreg1 <= accreg0;

		accreg4 <= accreg3;
		accreg5 <= accreg4;
		accreg0 <= accreg5;
	end if;
end process;

nco_phase_out <= accreg0(39 downto 8);
sin_out <= sin_pom;
cos_out <= cos_pom;

-- accumulator; latency 2
pacc : phase_acc
		port map (
			a => a_reg1,
			b => accreg1,
			clk => clk_dsp,
			s => accreg3);

-- sin tab; latency 1 
sinr : sinrom
		port map (
			clka => clk_dsp,
			addra => accreg5(31 downto 24),
			douta => sin_pom);

-- cos tab; latency 1			
cosr : cosrom
		port map (
			clka => clk_dsp,
			addra => accreg5(31 downto 24),
			douta => cos_pom);

end Behavioral;

